Host interrupt status, Register: 0x30 – Avago Technologies LSI53C1020 User Manual
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PCI Host Register Description
Version 2.4
Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Register: 0x30
Host Interrupt Status
Read/Write
The
register provides read-only interrupt status
information to the PCI Host. A write to this register of any value clears
the associated System Doorbell interrupt.
IOP Doorbell Status
31
The LSI53C1020 sets this bit when the IOP receives a
message from the system doorbell but has yet to process
it. The IOP processes the System Doorbell message by
clearing the corresponding system request interrupt.
Reserved
[30:4]
This field is reserved.
Reply Interrupt
3
The LSI53C1020 sets this bit when the Reply Post FIFO
is not empty. The LSI53C1020 generates a PCI interrupt
when this bit is set and the corresponding mask bit in the
register is cleared.
Reserved
[2:1]
This field is reserved.
System Doorbell Interrupt
0
The LSI53C1020 sets this bit when the IOP writes a
value to the System Doorbell. The host can clear this bit
by writing any value to this register. The LSI53C1020
generates a PCI interrupt when this bit is set and the cor-
responding mask bit in the
register
is cleared.
31 30
4
3
2
1
0
Host Interrupt Status
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
0