Avago Technologies LSI53C1020 - Manual (Page 42)

2-16 Functional Description
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
2.3.6 Power Management
The LSI53C1020 complies with the PCI Power Management Interface
Specification, Revision 1.1, and the PC2001 System Design Guide. The
LSI53C1020 supports the D0, D1, D2, D3
hot
, and D3
cold
power states.
D0 is the maximum power state, and D3 is the minimum power state.
Power State D3 is further categorized as D3
hot
or D3
cold
. Powering the
function off places it in the D3
cold
power state.
Bits [1:0] of the Power Management Control/Status register
independently control the power state of the PCI device on the
LSI53C1020.
Table 2.2 provides the power state bit settings.
The following sections describe the PCI Function Power States D0, D1,
D2, and D3. As the device transitions from one power level to a lower
one, the attributes that occur in the higher power state level carry into
the lower power state level. For example, Power State D2 includes the
attributes for Power State D1, as well as the attributes defined for Power
State D2. The following sections describe the PCI Function power states
in conjunction with the SCSI function.
2.3.6.1 Power State D0
Power State D0 is the maximum power state and is the power-up default
state for each function. The LSI53C1020 is fully functional in this state.
2.3.6.2 Power State D1
According to the PCI Power Management Interface Specification, Power
State D1 must have a power level equal to or lower than Power State D0.
Table 2.2 Power States
Power Management Control
and Status Register, Bits [1:0] Power State Function
0b00 D0 Maximum Power
0b01 D1 Snooze Mode
0b10 D2 Coma Mode
0b11 D3 Minimum Power