Avago Technologies LSI53C1020 - Manual (Page 157)

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual A-1
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Appendix A
Register Summary
Tables A.24 , A.25 , and A.26 provide a register summary.
Table A.24 LSI53C1020 PCI Registers
Register Name Offset
1
Read/Write Page
Vendor ID 0x00–0x01 Read Only 4-3
Device ID 0x02–0x03 Read Only 4-3
Command 0x04–0x05 Read/Write 4-3
Status 0x06–0x07 Read/Write 4-5
Revision ID 0x08 Read/Write 4-7
Class Code 0x09–0x0B Read Only 4-7
Cache Line Size 0x0C Read/Write 4-8
Latency Timer 0x0D Read/Write 4-8
Header Type 0x0E Read Only 4-9
Reserved 0x0F Reserved 4-9
I/O Base Address 0x10–0x13 Read/Write 4-9
Memory [0] Low 0x14–0x17 Read/Write 4-10
Memory [0] High 0x18–0x1B Read/Write 4-10
Memory [1] Low 0x1C–0x1F Read/Write 4-11
Memory [1] High 0x20–0x23 Read/Write 4-11
Reserved 0x24–0x27; 0x28–0x2B Reserved 4-12
Subsystem Vendor ID 0x2C–0x2D Read Only 4-13
Subsystem ID 0x2E–0x2F Read Only 4-14