Avago Technologies LSI53C1020 - Manual (Page 9)

Contents ix
Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
Cache Line Size 4-8
Latency Timer 4-8
Header Type 4-9
I/O Base Address 4-9
Memory [0] Low 4-10
Memory [0] High 4-10
Memory [1] Low 4-11
Memory [1] High 4-11
Subsystem Vendor ID 4-13
Subsystem ID 4-14
Expansion ROM Base Address 4-15
Capabilities Pointer 4-16
Interrupt Line 4-17
Interrupt Pin 4-17
Minimum Grant 4-18
Maximum Latency 4-18
Power Management Capability ID 4-19
Power Management Next Pointer 4-19
Power Management Capabilities 4-20
Power Management Control/Status 4-21
Power Management Bridge Support Extensions 4-22
Power Management Data 4-22
MSI Capability ID 4-22
MSI Next Pointer 4-23
Message Control 4-23
Message Address 4-25
Message Upper Address 4-25
Message Data 4-26
PCI-X Capability ID 4-26
PCI-X Next Pointer 4-27
PCI-X Command 4-27
PCI-X Status 4-29
4.2 I/O Space and Memory Space Register Descriptions 4-32
System Doorbell 4-34
Write Sequence 4-35
Host Diagnostic 4-36
Test Base Address 4-37
Diagnostic Read/Write Data 4-38