Comtech EF Data C5 - Manual (Page 18)

Table of Contents C5/K1/K3 Integrated Satellite Terminal System
xiv Rev. 0
Figure 4-25. EIA-422, EIA-232, or V.35 Master/Slave Clocking Diagram ...................................................... 4–74
Figure 4-26. Clock Slip...................................................................................................................................... 4–76
Figure 4-27. Doppler Shift................................................................................................................................. 4–77
Figure 5-1. M&C Block Diagram......................................................................................................................... 5-3
Figure 5-2. Modulator Block Diagram ................................................................................................................. 5-6
Figure 5-3. Demodulator Block Diagram ........................................................................................................... 5-10
Figure 5-4. Terrestrial Interface Block Diagram................................................................................................. 5-14
Figure 6-1. Fault Isolation Test Setup................................................................................................................... 6-2
Figure 6-2. Typical Output Spectrum (with Noise) .............................................................................................. 6-5
Figure 6-3. Typical Output Spectrum (without Noise) ......................................................................................... 6-5
Figure 6-4. Spectral Inversion .............................................................................................................................. 6-7
Figure 6-5. Typical Eye Constellations................................................................................................................. 6-8
Figure A-1. ASYNC/AUPC Block Diagram .......................................................................................................A–7
Figure A-2. Remote ASYNC Connection Diagram for Y Cable .......................................................................A–15
Figure A-3. Remote ASYNC Connection Diagram for Breakout Panel ............................................................A–16
Figure A-4. Sequential Decoder Block Diagram ...............................................................................................A–22
Figure A-5. Viterbi Decoder Block Diagram.....................................................................................................A–24
Figure A-6. Transmit Section of the Asymmetrical Loop Timing Block Diagram ............................................A–28
Figure A-7. Receive Section of the Asymmetrical Loop Timing Block Diagram..............................................A–29
Figure A-8. Reed-Solomon PCB .......................................................................................................................A–31
Figure A-9. Reed-Solomon Codec Block Diagram............................................................................................A–32
Figure A-10. Reed-Solomon Encoder Section Block Diagram..........................................................................A–33
Figure A-11. Reed-Solomon Code Page Format ...............................................................................................A–35
Figure A-12. Reed-Solomon Decoder Section Block Diagram .........................................................................A–36
Figure A-13. Reed-Solomon Codec Installation ................................................................................................A–39