AMD Geode LX 800@0.9W - Manual (Page 99)

AMD Geode™ LX Processors Data Book 99
CPU Core Register Descriptions 33234H
5.5 CPU Core Register Descriptions
All CPU Core registers are Model Specific Registers
(MSRs) and are accessed via the RDMSR and WRMSR
instructions.
Each module inside the processor is assigned a 256 regis-
ter section of the address space. The module responds to
any reads or writes in that range. Unused addresses within
a module’s address space are reserved, meaning the mod-
ule returns zeroes on a read and ignores writes. Addresses
that are outside all the module address spaces are invalid,
meaning a RDMSR/WRMSR instruction attempting to use
the address generates a General Protection Fault.
The registers associated with the CPU Core are the Stan-
dard GeodeLink™ Device MSRs and CPU Core Specific
MSRs. Table 5-12 and Table 5-13 are register summary
tables that include reset values and page references where
the bit descriptions are provided. Note that the standard
GLD MSRs for the CPU Core start at 00002000h.
Table 5-12. Standard GeodeLink™ Device MSRs Summary
MSR
Address Type Register Name Reset Value Reference
00002000h RO GLD Capabilities MSR (GLD_MSR_CAP) 00000000_000864xxh Page 108
00002001h R/W GLD Master Configuration MSR
(GLD_MSR_CONFIG) 00000000_00000320h Page 108
00002002h R/W GLD SMI MSR (GLD_MSR_SMI) - Not Used 00000000_00000000h Page 109
00002003h R/W GLD Error MSR (GLD_MSR_ERROR) - Not Used 00000000_00000000h Page 109
00002004h R/W GLD Power Management MSR (GLD_MSR_PM) -
Not Used 00000000_00000000h Page 109
00002005h R/W GLD Diagnostic Bus Control MSR
(GLD_MSR_DIAG) 00000000_00000000h Page 109
Table 5-13. CPU Core Specific MSRs Summary
MSR
Address Type Register Name Reset Value Reference
00000010h R/W Time Stamp Counter MSR (TSC_MSR) 00000000_00000000h Page 110
000000C1h R/W Performance Event Counter 0 MSR
(PERF_CNT0_MSR) 00000000_00000000h Page 110
000000C2h R/W Performance Event Counter 1 MSR
(PERF_CNT1_MSR) 00000000_00000000h Page 111
00000174h R/W SYSENTER/SYSEXIT Code Segment Selector
MSR (SYS_CS_MSR) 00000000_C09B0000h Page 112
00000175h R/W SYSENTER/SYSEXIT Stack Pointer MSR
(SYS_SP_MSR) 00000000_00000000h Page 113
00000176h R/W SYSENTER/SYSEXIT Instruction Pointer MSR
(SYS_IP_MSR) 00000000_00000000h Page 113
00000186h R/W Performance Event Counter 0 Select MSR
(PERF_SEL0_MSR 00000000_00000000h Page 114
00000187h R/W Performance Event Counter 1 Select MSR
(PERF_SEL1_MSR) 00000000_00000000h Page 114
00001100h R/W Instruction Fetch Configuration MSR
(IF_CONFIG_MSR) 00000000_00005051h Page 115
00001102h W IF Invalidate MSR (IF_INVALIDATE_MSR) 00000000_00000000h Page 118
00001108h R/W IF Test Address MSR (IF_TEST_ADDR_MSR) 00000000_00000000h Page 118
00001109h R/W IF Test Data MSR (IF_TEST_DATA_MSR) 00000000_xxxxxxxxh Page 119