15 sb cbc initialization vector 1 (sb_cbc_iv_1), 16 sb cbc initialization vector 2 (sb_cbc_iv_2), 17 sb cbc initialization vector 3 (sb_cbc_iv_3) – AMD Geode LX [email protected] User Manual
Page 528: 044h, Sb cbc initialization vector 1 (sb_cbc_iv_1), 00000000h, 048h, Sb cbc initialization vector 2 (sb_cbc_iv_2), 04ch, Sb cbc initialization vector 3 (sb_cbc_iv_3)
528
AMD Geode™ LX Processors Data Book
Security Block Register Descriptions
33234H
6.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1)
6.12.3.16 SB CBC Initialization Vector 2 (SB_CBC_IV_2)
6.12.3.17 SB CBC Initialization Vector 3 (SB_CBC_IV_3)
SB Memory Offset 044h
Type
R/W
Reset Value
00000000h
SB_CBC_IV_1 Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CBC_IV_1[63:32]
SB_CBC_IV_1 Bit Descriptions
Bit
Name
Description
31:0
IV[63:32]
CBC Initialization Vector 1 [63:32]. Bits [63:32] of the IV for the CBC AES mode.
Change this register only when both A and B channels are IDLE. (A and B start bits, SB
Memory Offset 000h and 004h, bit 0 = 0). This register must be programmed with the IV
prior to starting an AES CBC mode encryption or decryption.
SB Memory Offset 048h
Type
R/W
Reset Value
00000000h
SB_CBC_IV_2 Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CBC_IV_2[95:64]
SB_CBC_IV_2 Bit Descriptions
Bit
Name
Description
31:0
CBC_IV_2 [95:64]
CBC Initialization Vector 2 [95:64]. Bits [95:64] of the IV for the CBC AES mode.
Change this register only when both A and B channels are IDLE. (A and B start
bits, SB Memory Offset 000h and 004h, bit 0 = 0). This register must be pro-
grammed with the IV prior to starting an AES CBC mode encryption or decryption.
SB Memory Offset 04Ch
Type
R/W
Reset Value
00000000h
SB_CBC_IV_3 Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CBC_IV_3[127:96] (rev2.0)
SB_CBC_IV_3 Bit Descriptions
Bit
Name
Description
31:0
CBC_IV_3
[127:96]
CBC Initialization Vector 3 [127:96]. Bits [127:96] of the IV for the CBC AES Mode.
Change this register only when both A and B channels are IDLE. (A and B start bits, SB
Memory Offset 000h and 004h, bit 0 = 0). This register must be programmed with the IV
prior to starting an AES CBC mode encryption or decryption.