AMD Athlon 6 User Manual
Amd athlon™ processor model 6 revision guide
Table of contents
Document Outline
- AMD Athlon™ Processor Model 6
- Revision Guide
- AMD Athlon™ Processor Model 6 Revision Guide
- 1 Product Errata
- Table 1. CrossReference of Product Revision to Errata
- Table 2. Cross-Reference of Erratum to Processor Segments
- 16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addre...
- 17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to Memory- Mapped I/O
- 18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle
- 19 Processor Does Not Support Reliable Microcode Patch Mechanism
- 20 Processor Performance Counters Do Not Count Some x86 Instructions
- 21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution
- 22 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation
- 23 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults
- 24 Single Step Across I/O SMI Skips One Debug Trap
- 25 Software Prefetches May Report A Page Fault
- 2 Revision Determination
- 3 Technical and Documentation Support