AMD Geode LX 800@0.9W - Manual (Page 194)

194 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions 33234H
5.5.2.104 Bus Controller Extended Debug Registers 1 and 0 MSR (BXDR1_BXDR0_MSR)
5.5.2.105 Bus Controller Extended Debug Registers 3 and 2 MSR (BXDR3_BXDR2_MSR)
MSR Address 00001950h
Type R/W
Reset Value 00000000_00000000h
BXDR1_BXDR0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
BXDR1_PHYS_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BXDR0_PHYS_ADDR
BXDR1_BXDR0_MSR Bit Descriptions
Bit Name Description
63:32 BXDR1_PHYS_
ADDR Address Match Value for BXDR1. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
31:0 BXDR0_PHYS_
ADDR Address Match Value for BXDR0. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
MSR Address 00001951h
Type R/W
Reset Value 00000000_00000000h
BXDR3_BXDR2_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
BXDR3_PHYS_ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BXDR2_PHYS_ADDR
BXDR3_BXDR2_MSR Bit Descriptions
Bit Name Description
63:32 BXDR3_PHYS_
ADDR Address Match Value for BXDR3. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
31:0 BXDR2_PHYS_
ADDR Address Match Value for BXDR2. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)