AMD Geode LX 800@0.9W - Manual (Page 521)

AMD Geode™ LX Processors Data Book 521
Security Block Register Descriptions 33234H
6.12.3.2 SB Control B (SB_CTL_B)
0 STA Start for A Pointer. When set, this bit commands the AES to start a new operation
based on the current control register setting and the settings in SB Memory Offset 010h
and 014h. This bit is reset automatically when the operation completes. Setting this bit
also clears the “Complete” flag in the AES Interrupt register (SB Memory Offset
008h[16]) and in SB GLD_MSR_SMI (MSR 58002002h[32]). If an operation using the B
pointer set is already underway, the new operation for pointer set A will not start until the
previous B operation completes. If both A and B start bits are asserted in the same write
operation, the A operation take precedence.
SB Memory Offset 004h
Type
R/W
Reset Value 00000000h
SB_CTL_A Register Bit Descriptions (Continued)
Bit Name Description
SB_CTL_B Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RSVD
CBC
B
SCB DCB WK
B
ECB STB
SB_CTL_B Register Bit Descriptions
Bit Name Description
31:8 RSVD Reserved.
7:6 RSVD Reserved. These bits are implemented but reserved for future use. When writing to this
register, software should set these bits to 0 and ignore them on read.
5 CBCB Cipher Block Chaining (CBC) Mode for B Pointer. When set, the AES engine
encrypts/decrypts using the Cipher Block Chaining Mode for the B pointer. When reset,
the AES engine encrypts/decrypts using the Electronic Codebook (ECB) Mode. No ini-
tialization vector is used when in ECB mode.
4 SCB Source Coherency for B Pointer Set. When set, the source memory fetches using the
GLIU interface are flagged as coherent operations. When reset, the operations are non-
coherent.
3 DCB Destination Coherency for B Pointer Set. When set, the destination memory writes
using the GLIU interface are flagged as coherent operations. When reset, the operations
are non-coherent.
2 WKB Writable Key for B Pointer Set. When set, the AES engine uses the key from the Writ-
able Key register (SB Memory Offset 030h-03Ch) for its next operation. When reset, it
uses the hidden key value.
1 ECB Encrypt for B Pointer. When set, the AES operates in encryption mode. When reset, it
operates in decryption mode.
0 STB Start for B Pointer. When set, this bit commands the AES to start a new operation
based on the current control register setting and the settings in SB Memory Offset 020h
and 024h. This bit is reset automatically when the operation completes. Setting this bit
also clears the “Complete” flag in the AES Interrupt register (SB Memory Offset
008h[17]) and in the SB GLD_MSR_SMI (MSR 58002002h[33]). If an operation using
the A pointer set is already underway, the new operation for pointer set B will not start
until the previous A operation completes. If both A and B start bits are asserted in the
same write operation, the A operation take precedence.