AMD Geode LX 800@0.9W - Manual (Page 136)

136 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions 33234H
5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)
DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information
about debug conditions that have occurred. DR7 contains debug condition enables, types, and lengths. The contents of
debug registers are more easily accessed using the MOV instruction.
MSR Address 00001343h
Type R/W
Reset Value 00000000_FFFF0000h
DR7_DR6_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LEN3 TYPE3 LEN2 TYPE2 LEN1 TYPE1 LEN0 TYPE0 RSVD GD RSVD G3 L3 G2 L2 G1 L1 G0 L0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD (FFFFh) BT BS BD RSVD (FFh) B3 B2 B1 B0
DR7_DR6_MSR Bit Descriptions
Bit Name Description
63:62 LEN3 Breakpoint 3 Length.
61:60 TYPE3 Breakpoint 3 Type.
59:58 LEN2 Breakpoint 2 Length.
57:56 TYPE2 Breakpoint 2 Type.
55:54 LEN1 Breakpoint 1 Length.
53:52 TYPE1 Breakpoint 1 Type.
51:50 LEN0 Breakpoint 0 Length.
49:48 TYPE0 Breakpoint 0 Type.
47:46 RSVD Reserved.
45 GD Enable Global Detect Faults.
44:40 RSVD Reserved.
39, 38 G3, L3 Breakpoint 3 Enables.
37, 36 G2, L2 Breakpoint 2 Enables.
35, 34 G1, L1 Breakpoint 1 Enables.
33, 32 G0, L0 Breakpoint 0 Enables.
31:16 RSVD Reserved.
15 BT TSS T-Bit Trap Occured.
14 BS Single-Step Trap Occured.
13 BD Global Detect Fault Occured.
12:4 RSVD Reserved.
3 B3 Breakpoint 3 Matched.
2 B2 Breakpoint 2 Matched.
1 B1 Breakpoint 1 Matched.
0 B0 Breakpoint 0 Matched.