Table 8-30, Amd 3dnow!™ technology instruction set, Table 8-30. amd 3dnow!™ technology instruction set – AMD Geode LX [email protected] User Manual
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AMD Geode™ LX Processors Data Book
671
Instruction Set
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Table 8-30. AMD 3DNow!™ Technology Instruction Set
AMD 3DNow!™ Instructions
Opcode/imm8
Operation
Clk
Cnt
Notes
FEMMS Faster Exit of the MMX or
3DNow! State
0F0E
Tag Word <--- FFFFh (empties the floating point tag word)
MMX registers <--- undefined value
1
1
PAVGUSB Average of Unsigned Packed 8-Bit Values
2
MMX Register 1 with MMX Register2
0F0F [11 mm1
mm2] BF
MMX reg1 [byte] <--- rounded up --- (MMX reg 1 [byte] + MMX reg 2
[byte] + 01h)/2
MMX Register with Memory64
0F0F [mod mm r/m]
BF
MMX reg [byte] <--- rounded up --- (MMX reg 1 [byte] + Memory [byte]
+ 01h)/2
PF2ID Converts Packed Floating-Point Operand to Packed 32-Bit Integer
2
MMX Register 1 by MMX Register2
0F0F [11 mm1
mm2] 1D
MMX reg 1 [dword] <--- Sat integer --- MMX reg 2 [dword]
MMX Register 1 by Memory64
0F0F [mod mm r/m]
1D
MMX reg 1 [dword] <--- Sat integer --- Memory64 [dword]
PF2IW Packed Floating-Point to Integer Word Conversion with Sign Extend
2
MMX Register1 by MMX Register2
0F0F [11 mm1
mm2] 1C
MMX reg 1 [dword] <--- integer sign extended --- sat --- MMX reg 2
[dword]
MMX Register by Memory64
0F0F [mod mm r/m]
1C
MMX reg [dword] <--- integer sign extended --- sat --- Memory64
[dword]
PFACC Floating-Point Accumulate
2
MMX Register 1 with MMX Register2
0F0F [11 mm1
mm2] AE
MMX reg 1 [low dword] <--- MMX reg 1 [low dword] + MMX reg 1 [high
dword]
MMX reg 1 [high dword] <--- MMX reg 2 [low dword] + MMX reg 2 [high
dword]
MMX Register 1 with Memory64
0F0F [mod mm r/m]
AE
MMX reg 1 [low dword] <--- MMX reg 1[low dword] + MMX reg 1 [high
dword]
MMX reg 1 [high dword] <--- Memory64 [low dword] + Memory64 [high
dword]
PFADD Packed Floating-Point Addition
2
MMX Register1 with MMX Register2
0F0F [11 mm1
mm2] 9E
MMX reg 1[dword] <--- MMX reg 1 [dword] + MMX reg 2 [dword]
MMX Register1 with Memory64
0F0F [mod mm r/m]
9E
MMX reg 1 [dword] <--- MMX reg 1 [dword] + Memory64 [dword]
PFCMPEQ Packed Floating-Point Comparison, Equal to
2
MMX Register 1with MMX Register 2
0F0F [11 mm1
mm2] B0
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword] = MMX
reg 2 [dword])
MMX [dword] <--- 0000 0000 h --- if (MMX reg 1 [dword] NOT + MMX
reg 2 [dword])
MMX Register with Memory64
0F0F [mod mm r/m]
B0
MMX reg [dword] <--- FFFF FFFFh --- if (MMX reg [dword] =
Memory64 [dword])
MMX reg [dword] <---0000 0000h --- if (MMX reg [dword] NOT =
Memory64 [dword])
PFCMPGE Packed Floating-Point Comparison, Greater Than or Equal to
2
MMX Register 1 with MMX Register2
0F0F [11 mm1
mm2] 90
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword]
>
MMX
reg 2 [dword])
MMX reg 1 [dword] <---0000 0000h --- if (MMX reg 1 [dword] NOT
>
MMX reg 2 [dword])
MMX Register with Memory64
0F0F [mod mm r/m]
90
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1[dword]
>
Memory64 [dword])
MMX reg [dword] <--- 0000 0000h --- if (MMX reg [dword] NOT
>
Memory64 [dword])
PFCMPGT Packed Floating- Point Comparison, Greater Than
2
MMX Register1 with MMX Register2
0F0F [11 mm1
mm2] A0
MMX reg 1 [dword] <--- FFFF FFFFh --- if (MMX reg 1 [dword]
>
MMX
reg 2 [dword])
MMX reg 1 [dword] <---0000 0000h --- if (MMX reg 1 [dword] NOT
>
MMX reg 2 [dword])
MMX Register with Memory64
0F0F [mod mm r/m]
A0
MMX reg [dword] <---FFFF FFFFh --- if (MMX reg [dword]
>
Memory64
[dword])
MMX reg [dword] <--- 0000 0000h --- if (MMX reg [dword] NOT
>
Memory64 [dword])