AMD Geode LX [email protected] User Manual
Page 313
AMD Geode™ LX Processors Data Book
313
Display Controller Register Descriptions
33234H
DC_UNLOCK Bit Descriptions
Bit
Name
Description
31:16
RSVD
Reserved.
15:0
DC_UNLOCK
Unlock Code. This register must be written with the value 4758h in order to write to the
protected registers. The following registers are protected by the locking mechanism:
DC_GENERAL_CFG
(DC Memory Offset 004h)
DC_DISPLAY_CFG
(DC Memory Offset 008h)
DC_ARB_CFG
(DC Memory Offset 00Ch)
DC_FB_ST_OFFSET
(DC Memory Offset 010h)
DC_CB_ST_OFFSET
(DC Memory Offset 014h)
DC_CURS_ST_OFFSET
(DC Memory Offset 018h)
DC_VID_Y_ST_OFFSET
(DC Memory Offset 020h)
DC_VID_U_ST_OFFSET
(DC Memory Offset 024h)
DC_VID_V_ST_OFFSET
(DC Memory Offset 028h)
DC_LINE_SIZE
(DC Memory Offset 030h)
DC_GFX_PITCH
(DC Memory Offset 034h)
DC_VID_YUV_PITCH
(DC Memory Offset 038h)
DC_H_ACTIVE_TIMING
(DC Memory Offset 040h)
DC_H_BLANK_TIMING
(DC Memory Offset 044h)
DC_H_SYNC_TIMING
(DC Memory Offset 048h)
DC_V_ACTIVE_TIMING
(DC Memory Offset 050h)
DC_V_BLANK_TIMING
(DC Memory Offset 054h)
DC_V_SYNC_TIMING
(DC Memory Offset 058h)
DC_DFIFO_DIAG
(DC Memory Offset 078h)
DC_CFIFO_DIAG
(DC Memory Offset 07Ch)
DC_VID_DS_DELTA
(DC Memory Offset 080h)
DC_GLIU0_MEM_OFFSET
(DC Memory Offset 084h)
DC_DV_CTL
(DC Memory Offset 088h)
DC_GFX_SCALE
(DC Memory Offset 090h)
DC_IRQ_FILT_CTL
(DC Memory Offset 094h)
DC_FILT_COEFF1
(DC Memory Offset 098h)
DC_FILT_COEFF2
(DC Memory Offset 09Ch)
DC_VBI_EVEN_CTL
(DC Memory Offset 0A0h)
DC_VBI_ODD_CTL
(DC Memory Offset 0A4h)
DC_VBI_HOR_CTL
(DC Memory Offset 0A8h)
DC_VBI_LN_ODD
(DC Memory Offset 0ACh)
DC_VBI_LN_EVEN
(DC Memory Offset 0B0h)
DC_VBI_PITCH
(DC Memory Offset 0B4h)
DC_CLR_KEY
(DC Memory Offset 0B8h)
DC_CLR_KEY_MASK
(DC Memory Offset 0BCh)
DC_CLR_KEY_X
(DC Memory Offset 0C0h)
DC_CLR_KEY_Y
(DC Memory Offset 0C4h)
DC_GENLK_CTL
(DC Memory Offset 0D4h)
DC_VID_EVEN_Y_ST_OFFSET
(DC Memory Offset 0D8h)
DC_VID_EVEN_U_ST_OFFSET
(DC Memory Offset 0DCh)
DC_VID_EVEN_V_ST_OFFSET
(DC Memory Offset 0E0h)
DC_V_ACTIVE_EVEN_TIMING
(DC Memory Offset 0E4h)
DC_V_BLANK_EVEN_TIMING
(DC Memory Offset 0E8h)
DC_V_SYNC_EVEN_TIMING
(DC Memory Offset 0ECh)