Glcp clock active mask for suspend acknowledge, Glcp_clk4ack), 00000000_00000000h – AMD Geode LX [email protected] User Manual
Page 553
AMD Geode™ LX Processors Data Book
553
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2.11 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
6.14.2.12 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
MSR Address
4C000012h
Type
R/W
Reset Value
00000000_00000000h
GLCP_CLKDISABLE Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
VIPVIP
VIPG
LI
U
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AES
AESG
LIU
A
ESEE
GLCPDBG
GL
CP
GLI
U
GLCPPCI
VPV
OP
VPDO
T
_2
VPDO
T
_1
VPDO
T
_0
VPGLIU_1
VPGLIU_0
PCIPCIF
PCIPCI
PCIGLIU
GLIU1_1
GLIU1_0
DCGLIU_
1
DCGLIU_
0
RSVD
D
CDO
T
_
0
GLIU0_1
GLIU0_0
GP
GLMC
DRAM
BC_GLIU
BC_V
A
MSS
IPIPE
FPUF
AST
FPU
S
L
O
W
MSR Address
4C000013h
Type
R/W
Reset Value
00000000_00000000h
GLCP_CLK4ACK Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
V
IPVIP
VIPGLIU
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AES
AESGLIU
AESEE
GLCPDB
G
GLCPGLIU
G
L
CPPCI
VPV
O
P
VPDO
T
_2
VPDO
T
_1
VPDO
T
_0
VPG
LIU
_
1
VPG
LIU
_
0
PC
IP
C
IF
PCIPCI
PCIGLIU
GLIU
1_1
GLIU
1_0
DC
GL
IU
_
1
DC
GL
IU
_
0
RSVD
DCD
O
T
_
0
GLIU
0_1
GLIU
0_0
GP
GL
M
C
DR
A
M
BC_GLIU
BC_V
A
MSS
IPIPE
FPU
F
AST
FPUSLO
W