82 l1 data tlb entry msr (l1dtlb_entry_msr), 0000189ah, L1 data tlb entry msr (l1dtlb_entry_msr) – AMD Geode LX [email protected] User Manual
Page 177: 00000000_00000000h

AMD Geode™ LX Processors Data Book
177
CPU Core Register Descriptions
33234H
5.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR)
MSR Address
0000189Ah
Type
R/W
Reset Value
00000000_00000000h
L1DTLB_ENTRY_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LINADDR
RSVD
WP
WA
_
W
S
WC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PHYSADDR
RSVD
DIR
T
Y
AC
C
CD
WT
_B
R
US
WR
VA
L
ID
L1DTLB_ENTRY_MSR Bit Descriptions
Bit
Name
Description
63:44
LINADDR
Linear Address. Address [32:12].
43:35
RSVD (RO)
Reserved (Read Only).
34
WP
Write-protect Flag.
0: Page can be written.
1: Page is write-protected.
33
WA_WS
Write-allocate/Write-serialize Flag. If the page is cacheable, a 1 indicates the write-
allocate flag. If the page is non-cacheable, a 1 indicates the write-serialize flag.
32
WC
Write-combine Flag. When this page is marked as non-cacheable, a 1indicates that
writes may be combined before being sent to the bus.
31:12
PHYSADDR
Physical Address. Address [32:12]
11:7
RSVD (RO)
Reserved (Read Only).
6
DIRTY
Dirty Flag. A 1 indicates that the page has been written to.
5
ACC
Accessed Flag. A 1 indicates an entry in the TLB.
4
CD
Cache Disable Flag. A 1 indicates that the page is uncacheable.
3
WT_BR
Write-through/Write-burst Flag. When the page is cacheable, a 1 indicates that the
page is write-through. When the page is non-cacheable, a 1 indicates that the page
allows write bursting.
2
US
User Access Privileges.
0: Supervisor.
1: User.
1
WR
Writable Flag.
0: Page can not be written.
1: Page can be written.
0
VALID
Valid Bit. A 1 indicates that the entry in the TLB is valid.