AMD Geode LX 800@0.9W - Manual (Page 105)

AMD Geode™ LX Processors Data Book 105
CPU Core Register Descriptions 33234H
00001901h R/W Bus Controller Configuration 1 MSR
(BC_CONFIG1_MSR) 00000000_00000000h Page 184
00001904h RO Reserved Status MSR (RSVD_STS_MSR) 00000000_00000000h Page 185
00001908h R/W MSR Lock MSR (MSR_LOCK_MSR) 00000000_00000000h Page 185
00001910h R/W Real Time Stamp Counter MSR (RTSC_MSR) 00000000_00000000h Page 186
00001911h RO TSC and RTSC Low DWORDs MSR
(RTSC_TSC_MSR) 00000000_00000000h Page 186
00001920h R/W L2 Cache Configuration MSR (L2_CONFIG_MSR) 00000000_0000000Eh Page 187
00001921h RO L2 Cache Status MSR (L2_STATUS_MSR) 00000000_00000001h Page 188
00001922h R/W L2 Cache Index MSR (L2_INDEX_MSR) 00000000_00000000h Page 188
00001923h R/W L2 Cache Data MSR (L2_DATA_MSR) 00000000_00000000h Page 189
00001924h R/W L2 Cache Tag MSR (L2_TAG_MSR) 00000000_00000000h Page 189
00001925h R/W L2 Cache Tag with Increment MSR
(L2_TAG_I_MSR) 00000000_00000000h Page 190
00001926h R/W L2 Cache Built-In Self-Test MSR (L2_BIST_MSR) 00000000_00000000h Page 190
00001927h R/W L2 Cache Treatment Control MSR
(L2_TRTMNT_CTL_MSR) 00000000_00000000h Page 192
00001930h R/W Power Mode MSR (PMODE_MSR) 00000000_00000300h Page 193
00001950h R/W Bus Controller Extended Debug Registers 1 and 0
MSR (BXDR1_BXDR0_MSR) 00000000_00000000h Page 194
00001951h R/W Bus Controller Extended Debug Registers 3 and 2
MSR (BXDR3_BXDR2_MSR) 00000000_00000000h Page 194
00001953h R/W Bus Controller Extended Debug Registers 6 and 7
MSR (BXDR6_BXDR7_MSR) 00000000_00000000h Page 195
00001970h R/W Bus Controller Debug Register 0 MSR
(BDR0_MSR) 00000000_00000000h Page 197
00001971h R/W Bus Controller Debug Register 1 MSR
(BDR1_MSR) 00000000_00000000h Page 197
00001972h R/W Bus Controller Debug Register 2 MSR
(BDR2_MSR) 00000000_00000000h Page 197
00001973h R/W Bus Controller Debug Register 3 MSR
(BDR3_MSR) 00000000_00000000h Page 197
00001976h R/W Bus Controller Debug Register 6 MSR
(BDR6_MSR) 00000000_00000000h Page 198
00001977h R/W Bus Controller Debug Register 7 MSR
(BDR7_MSR) 00000000_00000000h Page 198
00001980h R/W Memory Subsystem Array Control Enable MSR
(MSS_ARRAY_CTL_EN_MSR) 00000000_00000000h Page 200
00001981h R/W Memory Subsystem Array Control 0 MSR
(MSS_ARRAY_CTL0_MSR) 00000000_2010F3C9h Page 200
00001982h R/W Memory Subsystem Array Control 1 MSR
(MSS_ARRAY_CTL1_MSR) 00000000_104823CFh Page 201
00001983h R/W Memory Subsystem Array Control 2 MSR
(MSS_ARRAY_CTL2_MSR) 00000104_820C30C3h Page 201
00001A00h R/W FPU Modes MSR (FP_MODE_MSR) 00000000_00000000h Page 202
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address Type Register Name Reset Value Reference