74 x86 control registers msrs (cr1, cr2, cr3, cr4), 75 data cache index msr (dc_index_msr), 00001881h – AMD Geode LX [email protected] User Manual
Page 172: X86 control register 1 msr (cr1_msr), 00000000_xxxxxxxxh, Data cache index msr (dc_index_msr)
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AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4)
These are the standard x86 Control Registers CR1, CR2, CR3, and CR4. CR0 is located at MSR 00001420h (see Section
5.5.2.50 on page 149). The contents of CR0-CR4 should only be accessed using the MOV instruction. They are mentioned
here for completeness only. See Section 5.4.1 “Control Registers” on page 95 for bit descriptions
x86 Control Register 1 MSR (CR1_MSR)
x86 Control Register 2 MSR (CR2_MSR)
x86 Control Register 3 MSR (CR3_MSR)
x86 Control Register 4 MSR (CR4_MSR)
5.5.2.75 Data Cache Index MSR (DC_INDEX_MSR)
MSR Address
00001881h
Type
R/W
Reset Value
00000000_xxxxxxxxh
MSR Address
00001882h
Type
R/W
Reset Value
00000000_xxxxxxxxh
MSR Address
00001883h
Type
R/W
Reset Value
00000000_xxxxxxxxh
MSR Address
00001884h
Type
R/W
Reset Value
00000000_xxxxxxxxh
MSR Address
00001890h
Type
R/W
Reset Value
00000000_00000000h
DC_INDEX_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
D
C
_DSEL
RSVD
DC_LINE
DC_WAY
DC_INDEX_MSR Bit Descriptions
Bit
Name
Description
63:18
RSVD (RO)
Reserved (Read Only).
17:16
DC_DSEL
Data QWORD Select. Determines which QWORD in a cache line is accessed by a read
or a write to DC_DATA_MSR (MSR 00001891h). DC_DSEL increments on accesses to
DC_DATA and resets to 0 on accesses to DC_TAG_MSR (MSR 00001892h) or
DC_TAG_I_MSR (MSR 00001893h).
15:11
RSVD (RO)
Reserved (Read Only).
10:4
DC_LINE
Cache Line Select. Forms the high 7 bits of a 9-bit counter. The DC_WAY field (bits
[1:0]) forms the low 2 bits of the counter. This field increments when DC_WAY overflows
on an access to DC_TAG_I_MSR (MSR 00001893h).
3:0
DC_WAY
Cache Way Select. Forms the low 2 bits of a 9-bit counter. The DC_LINE field (bits
[10:4]) forms the high 7 bits of the counter. This field post-increments on accesses to
DC_TAG_I_MSR (MSR 00001893h).