84 l2 tlb/dte/pte index msr (l2tlb_index_msr), 0000189bh, 00000000_00000000h – AMD Geode LX [email protected] User Manual
Page 178: 0000189ch, L2 tlb/dte/pte index msr (l2tlb_index_msr)
178
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR)
Bit descriptions for this register are the same as for MSR 0000189Ah, except read/write of this register causes an auto-
increment on the L1 TLB_INDEX_MSR (MSR 00001898h).
5.5.2.84 L2 TLB/DTE/PTE Index MSR (L2TLB_INDEX_MSR)
MSR Address
0000189Bh
Type
R/W
Reset Value
00000000_00000000h
L1DTLB_ENTRY_I_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LINADDR
RSVD
WP
WA
_
W
S
WC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PHYSADDR
RSVD
DIR
T
Y
AC
C
CD
WT
_B
R
US
WR
VA
L
ID
MSR Address
0000189Ch
Type
R/W
Reset Value
00000000_00000000h
L2TLB_INDEX_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
SEL
RSVD
INDEX
WA
Y
INDEX
L2TLB_INDEX_MSR Bit Descriptions
Bit
Name
Description
If SEL (bits [17:16]) = 0x
63:18
RSVD (RO)
Reserved (Read Only). (Default = 0)
17:16
SEL
Select Array to Access.
0x: L2 TLB (64 entries, values 0-63).
10: DTE cache (12 entries, values 0-11).
11: 4M PTE cache (4 entries, values 0-3).
15:6
RSVD (RO)
Reserved (Read Only). (Default = 0)
5:1
INDEX
L2 TLB Index. Post-increments on an access to L2TB_ENTRY_I_MSR (MSR
0000189Fh) if WAY (bit 0) = 1.
0
WAY
Way to Access. Toggles on each access to L2TB_ENTRY_I_MSR (MSR 0000189Fh).
If SEL (bits [17:16]) = 1x
63:18
RSVD (RO)
Reserved (Read Only). (Default = 0)
17:16
SEL
Select Array to Access.
0x: L2 TLB (64 entries, values 0-63).
10: DTE cache (12 entries, values 0-11).
11: 4M PTE cache (4 entries, values 0-3).