AMD Geode LX [email protected] User Manual
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546
AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor Register Descriptions
33234H
28
GLCPDBG
GLCP Debug Clock Off. When set, disables GLCP DBG logic clock.
27
GLCPGLIU
GLCP GLIU Clock Off. When set, disables GLCP GLIU clock.
26
GLCPPCI
GLCP GIO PCI Clock Off. When set, disables GLCP’s GIO PCI clock.
25
VPVOP
VP VOP Clock Off. When set, disables VOP logic clock.
24
VPDOT_2
VP Dot Clock 2 Off. When set, disables VP Dot Clock 2 (vp_vid).
23
VPDOT_1
VP DOT Clock 1 Off. When set, disables VP Dot Clock 1 (lcd_pix).
22
VPDOT_0
VP DOT Clock 0 Off. When set, disables VP Dot Clock 0 (vp_pix).
21
VPGLIU_1
VP GLIU Clock 1 Off. When set, disables VP GLIU Clock 1 (lcd).
20
VPGLIU_0
VP GLIU Clock 0 Off. When set, disables VP GLIU Clock 0 (vp).
19
PCIPCIF
Fast PCI Clock Off. When set, disables fast PCI clock inside GLPCI block.
18
PCIPCI
PCI Clock Off. When set, disables normal PCI clock inside GLPCI block.
17
PCIGLIU
GLPCI Clock Off. When set, disables clock entering GLPCI block.
16
GLIU1_1
GLIU1 Clock Off. When set, disables main clock to secondary GLIU.
15
GLIU1_0
GLIU1 Timer Logic Clock Off. When set, disables clock to timer logic of secondary
GLIU.
14
DCGLIU_1
DC GLIU clock 1 Off. When set, disables DC GLIU Clock 1 (vga).
13
DCGLIU_0
DC GLIU clock 0 Off. When set, disables DC GLIU Clock 0 (DC).
12
RSVD
Reserved. Unused bit, reads what was written, value written has no effect.
11
DCDOT_0
DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC).
10
GLIU0_1
GLIU0 Clock Off. When set, disables main clock to primary GLIU.
9
GLIU0_0
GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary
GLIU.
8
GP
GP Clock Off. When set, disables GP clock (GLIU).
7
GLMC
GLMC Clock Off. When set, disables GLIU clock to GLMC.
6
DRAM
DRAM Clocks Off. When set, disables external DRAM clocks (and, hence, feedback
clocks).
5
BC_GLIU
Bus Controller Clock Off. When set, disables clock to CPU bus controller block.
4
BC_VA
CPU to Bus Controller Clock Off. When set, disables CPU clock to bus controller
block.
3
MSS
CPU to MSS Clock Off. When set, disables CPU clock to memory subsystem block.
2
IPIPE
CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block.
1
FPUFAST
FPU Fast Clock Off. When set, disables the fast FPU clock.
0
FPUSLOW
FPU Clock Off. When set, disables the slow CPU clock to FPU.
GLCP_PMCLKDISABLE Bit Descriptions (Continued)
Bit
Name
Description