Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 99)

Management Complex
ATCA-9305 User’s Manual (10009109-07) 99
4.2 Memory
The memory devices in the management complex consist of:
 1 GB DDR2 SDRAM
 512 KB socketed flash
 8 MB soldered NOR flash (two redundant banks of 4 MB each)
 1 GB soldered NAND flash (optional)
 512 Mb or 64 MB soldered NOR flash
4.2.1 SDRAM
This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory module
(SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus operating at
200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a nibble and
corrects all single-bit errors.
The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module consists
of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL) clock, and
a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical address
0000,0000
16.
4.2.2 Flash
There are several flash devices on the local bus interfacing the CPLD and MPC8548 processor.
The four soldered flash banks are labeled 1 through 4:
 Banks 1 and 2 are the MPC8548 U-boot banks (see “ 4M ”). These boot banks are used in the
boot redirection scheme, see “ BOOT DEVICE REDIRECTION (BDR) .”
 Banks 3 and 4 are physically one device, but appear in the software as two banks of 32 MB
(see “
64 MB ”). These are for general purpose storage.
4.2.2.1 512 KB
The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,0000
16
and is used for
Engineering code. The StrataFlash (P33) features high-performance fast asynchronous access
times, low power, and flexible security options.