Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 115)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 115
5.1.14 Reset Command Sticky #1
The read/write Reset Command Sticky #1 register forces one of several types of the group-
complex resets, as shown below. A reset sequence is first initiated by writing a one to one or
more bits, then the PLD performs that particular reset. The bit will persist until cleared.
1 reserved
0 reserved
Table 5-14 Reset Command 5 (0x34) (continued)
Bits Function Description
The board powers down and powers back up when the Cavium processors power is back up
(bits 0 or 1 are cleared).
Table 5-15 Reset Command Sticky #1 (0x38)
Bits Function Description
7 CAV1C Cavium 1 Complex reset
6 CAV2C Cavium 2 Complex reset
5 SWIC Switch Complex reset
4 CAV1CF Cavium 1 Complex 4MB Flash reset
3 CAV2CF Cavium 2 Complex 4MB Flash reset
2 NANDF NAND Flash reset
1 CAV2RPD Reset and power down the Cavium 2 core
0 CAV1RPD Reset and power down the Cavium 1 core