Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 124)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 124
5.1.27 Cavium GPIO Data In
This register reads the value on the GPIO lines connected to each Cavium.
4 P2GPIO4 Set the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Set the value of the Cavium 2 GPIO bit 3
2 reserved
1 P1GPIO4 Set the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Set the value of the Cavium 1 GPIO bit 3
Table 5-27 Cavium GPIO Data Out (0x84) (continued)
Bits Function Description
Table 5-28 Cavium GPIO Data In (0x88)
Bits Function Description
7 reserved
6 reserved
5 reserved
4 P2GPIO4 Read the value of the Cavium 2 GPIO bit 4
3 P2GPIO3 Read the value of the Cavium 2 GPIO bit 3
2 reserved
1 P1GPIO4 Read the value of the Cavium 1 GPIO bit 4
0 P1GPIO3 Read the value of the Cavium 1 GPIO bit 3