Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 81)

Cavium Processor Complex
ATCA-9305 User’s Manual (10009109-07) 81
3.5 Memory
The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices. SCP variants do not support RLDRAM.
3.5.1 DDR2 SDRAM
The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is up to 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM provides
the serial presence detection (SPD). On-card SDRAM occupies physical addresses from
0,0000,0000,0000
16
to 0,0003,FFFF,FFFF
16
.
Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.
spi_num_ports
undefined Defines the number logical ports per SPI interface. Possible
values are 1 (default) and 16. If set to 16, additional logical
network interfaces are generated named octspi0.1, octspi0.2,
... octspi0.15 and octspi1.1, octspi1.2, ..., octspi1.15 for logical
ports 1 .. 15 on SPI interface 0 and 1 respectively.
octspi0/octspi1 use port number 0.
The commands eth_eg_map, eth_ig_map and eth_map_show
are available in the 16-port configuration for mapping ports to
ethernet VLANs and vice versa.
Table 3-6 Standard Cavium Environment Variables (continued)
Variable Default Value Description