Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 72)

Cavium Processor Complex
ATCA-9305 User’s Manual (10009109-07) 72
3.2 PCI
The Cavium is a slave device on the PCI bus. The Cavium U-boot monitor image is provided by
the MPC8548 management processor via PCI. The MPC8548 monitors the Cavium boot status
and has the ability to try alternate boot images if the current one fails.
The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release
register.
3.2.1 CN5860 Boot Over PCI
The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up, the
CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management processor
performs the following steps:
1. Initialize the CN5860 RAM.
2. Copy the CN5860 U-boot to the CN5860 RAM.
3. Copy boot code to the reset vector to jump to the U-boot code in RAM.
4. Release the CN5860 processor cores from reset.
5. Receive return codes from the CN5860 that indicate any boot or POST errors and take the
appropriate action.
The management processor (MPC8548) monitor implements a utility to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.
The U-boot command "oct_moninit" can be used to program a binary boot image for the
Octeon processors into the boot flash device of the management CPU. The management
processor will use this image to start up the Octeon processors.
Syntax:
oct_moninit [.]