Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 122)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 122
5.1.24 JTAG
This register allows for manual reprogramming of the PLDs on the board. Changes to this
register do not take effect until after a full board reset.
4 P1CMUL4 These bits drive directly to the Cavium 2. The core clock
speed is the number multiplied by 50 MHz. For example, the
800 MHz core is set to 16(0x10).
3 P1CMUL3
2 P1CMUL2
1 P1CMUL1
0 P1CMUL0
Table 5-24 Cavium 2 C_MULL Clock Divisor Control (0x74) (continued)
Bits Function Description
Table 5-25 JTAG (0x78)
Bits Function Description
7 reserved
6 reserved
5 JTAGOEN JTAG Output Enable
4 JTAGTCKSEL JTAG Test Clock Select changes from header to PLD as the TCK
source
3 JTAGTCK JTAG Test Clock
2 JTAGTMS JTAG Test Mode Select
1 JTAGTDO JTAG Test Data Output
0 JTAGTDI JTAG Test Data Input (read only)