Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 112)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 112
5.1.9 Reset Command 1
The write-only Reset Command 1 register forces one of several types of resets, as shown below.
A reset sequence is first initiated by writing a one to a single valid bit, then the PLD performs
that particular reset, and the bit is automatically cleared.
5.1.10 Reset Command 2
The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
0 FPPB Front Panel Push Button (FP_PSH_BUTTN, POR_RST)
Table 5-9 Reset Event (0x20) (continued)
Bits Function Description
Table 5-10 Reset Command 1 (0x24)
Bits Function Description
7 WBR Reset the Whole Board
6 PQCR Reset the MPC8548 Complex
5 CAV1CR Reset the Cavium CN5860 1 Complex
4 CAV2CR Reset the Cavium CN5860 2 Complex
3 SWICR Reset the switch BCM5680x Complex
2 I2C R Reset the I2C on the MPC8548
1 RTMR Reset the (optional) RTM
0 reserved
Table 5-11 Reset Command 2 (0x28)
Bits Function Description
7 PQHR MPC8548 Hardware Reset
6 PQSR MPC8548 Software Reset