Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 120)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 120
5.1.21 RTM Status
The RTM identification (ID) is determined by factory installed configuration resistors.
5.1.22 Cavium 1 C_MUL Clock Divisor Control
Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.
Table 5-22 RTM Control (0x68)
Bits Function Description
7 0
6 0
5 0
4 RTMP RTM is Present
3 RTMID0 RTM Identification bits 0:3
0000 = Test RTM (factory only)
1000 = 18GbE I/O RTM
1100 = 12GbE and 2x10GbE I/O RTM
0111 - ARTM-9305 6X10GB
1001 - ARTM-9305 Flash
2 RTMID1
1 RTMID2
0 RTMID3
Do not over-clock the Cavium frequency (bits 6:7 hard strapped).