Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 83)

Cavium Processor Complex
ATCA-9305 User’s Manual (10009109-07) 83
3.6 StratixGX Interconnect
The Altera StratixGX FPGA provides the high-speed SPI-4.2 interconnect. Each complex has
dual SPI-to-XAUI bridges connected to the XAUI Ethernet switch ports.
3.6.1 PLD Registers
The FPGA bridge is located at address 0x1D030000. Use the following registers to access the
XAUI to SPI bridge configuration registers.
3.6.1.1 Data Registers
PLD registers information can be requested via sales/marketing office.
Table 3-8 Data 31:24 (0x0)
Bits R/W Function
7 R/W Data 31
6 R/W Data 30
5 R/W Data 29
4 R/W Data 28
3 R/W Data 27
2 R/W Data 26
1 R/W Data 25
0 R/W Data 24