beautypg.com

11 reset command 3, Table 5-12, Reset command 3 (0x2c) – Artesyn ATCA-9305 User's Manual (May 2014) User Manual

Page 113: Management processor cpld

background image

Management Processor CPLD

ATCA-9305 User’s Manual (10009109-07)

113

5.1.11 Reset Command 3

The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.

5

PQDR

MPC8548 DDR SDRAM Reset

4

PQF

MPC8548 Flash reset

3

NANDR

MPC8548 NAND flash Reset

2

NANDWR

MPC8548 NAND flash Warm Reset

1

reserved

0

reserved

Table 5-11 Reset Command 2 (0x28) (continued)

Bits

Function

Description

Table 5-12 Reset Command 3 (0x2C)

Bits

Function

Description

7

CAV1R

Cavium 1 Reset

6

CAV1PR

Cavium 1 PCI Reset

5

CAV1DR

Cavium 1 DDR SDRAM Reset

4

CAV1F

Cavium 1 4 MB Flash (Cavium local bus) reset

3

CAV1M1

Cavium 1 MIP1 reset

2

CAV1M2

Cavium 1 MIP2 reset

1

reserved

0

reserved