Artesyn ATCA-9305 User's Manual (May 2014) - Manual (Page 117)

Management Processor CPLD
ATCA-9305 User’s Manual (10009109-07) 117
5.1.17 Miscellaneous Control
This register includes two bits for manually toggling the MPC8548 I 2 C bus.
4 BSJ Boot from Socket Jumper A shunt on J9 [1:2] selects the 512KB
socketed ROM as the boot device, see
Figure 2-11 .
3 NFBS Nand Flash Busy Signal
2 BDS Active boo t device is socket
1 BDF1 Active boot device is flash 2
0 BDF0 Active boot device is flash 1
Table 5-17 Boot Device Redirection (0x50) (continued)
Bits Function Description
Table 5-18 Miscellaneous Control (0x54)
Bits Function Description
7 P33WP 0 Write Protect disabled (default until the monitor boots)
1 Write Protect enabled
6 SROM1WP 0 Write Protect disabled
1 Write Protect enabled (default)
5 SROM0WP 0 Write Protect disabled
1 Write Protect enabled (default)
4 FLASH1WP 0 Write Protect disabled (default until the monitor boots)
1 Write Protect enabled
3 FLASH0WP 0 Write Protect disabled (default until the monitor boots)
1 Write Protect enabled
2 NANDWP 0 Write Protect disabled
1 Write Protect enabled (default)
1 I2CSDA I
2 C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line