9 gliu control registers, 1 dc gliu0 memory offset (dc_gliu0_mem_offset), 2 dc dirty/valid ram control (dc_dv_ctl) – AMD Geode LX [email protected] User Manual

Page 339: Dc gliu0 memory offset (dc_gliu0_mem_offset), Dc dirty/valid ram control (dc_dv_ctl)

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9 gliu control registers, 1 dc gliu0 memory offset (dc_gliu0_mem_offset), 2 dc dirty/valid ram control (dc_dv_ctl) | Dc gliu0 memory offset (dc_gliu0_mem_offset), Dc dirty/valid ram control (dc_dv_ctl) | AMD Geode LX [email protected] User Manual | Page 339 / 680

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