Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 192)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 192
Table 6-65 Telecom Clock Monitor Frequency/Period Register
0x6A -0x6B
Bit Description Default Access
15:0 Result of supervised Telecom Clock.
Gate mode:
0: No clock edge sampled. Clock to slow for time base.
1 - 65534: Number of sampled clocks during timer base.
65535: Overflow. Clock to fast for time base.
Period Mode
0: No clock edge sampled. Clock to fast for time base.
1 - 65534: Number of clocks during one supervised clock period.
65535: Overflow. Supervised clock to slow for time base.
Note: Only valid when corresponding bit in
Table "Telecom Clock
Monitor Status Register" on page 188 is set.
0 LPC: r
Table 6-66 Telecom Clock Monitor Lower Limit Register
Address: 0x6C -0x6D
Bit Description Default Access
15:0 Lower limit for supervised Telecom Clock:
Used by
Table "Telecom Clock Monitor Out of Range Register" on
page 189 .
0 LPC: r/w
Table 6-67 Telecom Clock Monitor Upper Limit Register
Address: 0x6E -0x6F
Bit Description Default Access
15:0 Upper limit for supervised Telecom Clock:
Used by
Table "Telecom Clock Monitor Out of Range Register" on page
189 .
0 LPC: r/w