Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 158)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 158
6.4.10.2 Reset Mask Register
The reset mask register enables or disables forwarding of a reset source to reset output signal.
Only Push Button Reset requests are masked using the reset mask register. The register default
values are latched when PWR_GOOD is asserted. This register can be read or written by the
host CPU. 1 in the register bit indicates that the associated reset is enabled. 0 indicates that the
associated reset source is masked.
Table 6-19 BIOS Reset Source Register
Address Offset: 0x10
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 LPC: r/w1c
IPMC: r
1 XDPx reset request (Any one of XDPx signal caused reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
3 PCH_WDT_TOUT_ reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
5 INTEL_INIT3V3_ PCH output
1: Event Occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
6 PCH_PLTRST_ reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
Table 6-20 Reset Mask Register
Address Offset: 0x11
Bit Description Default Access
1:0 Reserved 0 r