Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 164)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 164
6.4.10.9 DIMM ADR Configuration Register
The DIMM ADR Configuration Register enables or disables the ADR feature. Each bit of this
register corresponds to a reset source. When a bit is set, it enables the ADR for the
corresponding reset signal. Upon receiving a reset event, FPGA reset logic looks if the ADR is
enabled for that particular reset. When enabled, PCH_ADR_IRQ_ signal is asserted and
PCH_SYS_RST_ is generated after a delay of 30 us. If ADR is not enabled PCH_SYS_RST_ is
generated immediately without the assertion of PCH_ADR_IRQ_ signal.
Table 6-27 DIMM ADR Feature Configuration Register
Address Offset: 0x18
Bit Description Default Access
0 ADR enable for Push button reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r/w
1 ADR enable for RTM Push button
reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r/w
2 ADR enable for IPMI reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r/w
3 ADR enable for watchdog reset
PCH_WDT_TOUT_
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r/w
4 ADR enable for software reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r/w
7:5 Reserved 0 r