Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 161)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 161
6.4.10.6 OS IPMC Watchdog Timeout Register
When one of the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is set, the
corresponding OS IPMC Watchdog Timeout Register bit is set. The OS clears this status bit by
writing 1.
Table 6-23 Reset Source Register
Address Offset: 0x14
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 LPC: r/w1c
IPMC: r
1 XDPx reset request (Any one of XDPx signal caused reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
3 PCH_WDT_TOUT_ reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
5 INTEL_INIT3V3_ PCH output
1: Event occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
6 PCH_PLTRST_ reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
BIOS should never write to this register.