Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 177)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 177
6.4.14 BIOS Boot Mode Register
6.4.15 Update Channel Equalization Control Register
Table 6-42 BIOS Boot Mode Register
Address Offset: 0x43
Bit Description Default Access
0
1
The switch signals SW_BIOS[1:0] controls the BIOS Boot Mode: Ext.
1: SW4.3 ON
0: SW4.3 OFF r
Ext.
1: SW4.4 ON
0: SW4.4 OFF r
7:2 Reserved 0 r
Table 6-43 Update Channel Equalization Control Register
Address Offset: 0x48
Bit Description Default Access
0 Control output Signal UC1_EQ_RX:
0: UC1_EQ_RX is driven low
1: UC1_EQ_RX is tri-state 0 LPC: r/w
IPMC: r
1 Control output Signal UC1_EQ_TX:
0: UC1_EQ_TX is driven low
1: UC1_EQ_TX is tri-state 0 LPC: r/w
IPMC: r
2 Control output Signal UC2_EQ_RX:
0: UC2_EQ_RX is driven low
1: UC2_EQ_RX is tri-state 0 LPC: r/w
IPMC: r