16 ipmc e-keying status register, Table 6-44, Ipmc e-keying status register – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 178: Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
178
6.4.16 IPMC E-Keying Status Register
3
Control output Signal UC2_EQ_TX:
0: UC2_EQ_TX is driven low
1: UC2_EQ_TX is tri-state
0
LPC: r/w
IPMC: r
4
Control output Signal UC3_EQ_RX:
0: UC3_EQ_RX is driven low
1: UC3_EQ_RX is tri-state
0
LPC: r/w
IPMC: r
5
Control output Signal UC3_EQ_TX:
0: UC3_EQ_TX is driven low
1: UC3_EQ_TX is tri-state
0
LPC: r/w
IPMC: r
6
Control output Signal UC4_EQ_RX:
0: UC4_EQ_RX is driven low
1: UC4_EQ_RX is tri-state
0
LPC: r/w
IPMC: r
7
Control output Signal UC4_EQ_TX:
0: UC4_EQ_TX is driven low
1: UC4_EQ_TX is tri-state
0
LPC: r/w
IPMC: r
Table 6-43 Update Channel Equalization Control Register (continued)
Address Offset: 0x48
Bit
Description
Default
Access
Table 6-44 IPMC E-Keying Status Register
Address Offset: 0x49
Bit
Description
Default
Access
4:0
IPMC_UPDCH_[4:0]. IPMC electronic key signals.
Ext.
LPC: r
5
IPMC_FAB1_10G_SEL_
Ext.
LPC: r
6
IPMC_FAB2_10G_SEL_
Ext.
LPC: r
7
Reserved
0
r