Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 157)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 157
6.4.9 DIMM ADR Status Register
BIOS can read the status of PCH_ADR_IRQ_ signal from this register on boot up. This gives BIOS
the information that the DIMM has data stored from last boot. BIOS must clear this register
after boot up. Writing 1 to this register bit clears the register bit.
6.4.10 Reset Registers
6.4.10.1 BIOS Reset Source Register
The BIOS Reset Source Register stores the source of the most recent reset. 1 in the register bit
indicates that the associated reset has occurred. If more than one reset occurs from different
sources without clearing the corresponding register bits, one cannot determine the most
recent reset source since more than one bit will be set. The same situation occurs, if two reset
sources go active at the same time.
Table 6-18 DIMM ADR Status Register
Address Offset: 0x0A
Bit Description Default Access
0 Indicates if the ADR feature is enabled. (GPIO31 of
Cavecreek)
0: ADR disabled (PCH_ADR_IRQ_ is driven high)
1: ADR enabled (PCH_ADR_IRQ_ is driven low) PWR_GOOD:0 LPC: r/w1c
IPMC: r
7:1 Reserved 0 r
OS should never write to this register.