21 dimm event register, Table 6-49, Dimm event register – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 181: Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
181
6.4.21 DIMM Event Register
4
Signal level of FPGA_SW1.4 (Connected to
SW1.4)
Ext
r
5
Signal level of FPGA_SW3_4 (Connected to
SW3.4)
Ext
r
7:6
Reserved
0
r
Table 6-48 Spare Signal Status Register (continued)
Address Offset: 0x52
Bit
Description
Default
Access
Table 6-49 DIMM Event Register
Address Offset: 0x53
Bit
Description
Default
Access
0
Shows the status of DIMM Event signal from CPU0 Channel 0/A
Ext.
r
1
Shows the status of DIMM Event signal from CPU0 Channel 1/B
Ext.
r
2
Shows the status of DIMM Event signal from CPU0 Channel 2/C
Ext.
r
3
Shows the status of DIMM Event signal from CPU0 Channel 3/D Ext.
r
4
Shows the status of DIMM Event signal from CPU1 Channel 0/E
Ext.
r
5
Shows the status of DIMM Event signal from CPU1 Channel 1/F
Ext.
r
6
Shows the status of DIMM Event signal from CPU1 Channel 2/G
Ext.
r
7
Shows the status of DIMM Event signal from CPU1 Channel 3/H Ext.
r