Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 163)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 163
6.4.10.8 IPMC Reset Source Register
The IPMC Reset Source Register stores the source of the most recent reset. 1 in the register bit
indicates that the associated reset has occurred. If more than one reset occurs from different
sources without clearing the corresponding register bits, one cannot determine the most
recent reset source since more than one bit will be set. The same situation occurs, if two reset
sources are active at the same time.
Table 6-26 IPMC Reset Source Register
Address Offset: 0x17
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 IPMC: r/w1c
1 XDPx reset request (Any one of XDPx signal caused reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
3 PCH_WDT_TOUT_ reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
5 INTEL_INIT3V3_ PCH output
1: Event Occurred PWR_GOOD:0 IPMC: r/w1c
6 PCH_PLTRST_ reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c