Table 6-40, Default boot spi flash write enable, Table 6-41 – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 176: Recovery boot spi flash write enable, Table "recovery boot spi flash write enable" on, Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
176
Write protection status signals for the Boot SPI flashes are determined by external switch
settings SW1.1and SW1.2. Software can overwrite the status of the write protection status by
writing a magic word to the Boot SPI Flash Write Enable Registers.
1. The default is latched from SW1.1 when PCH_PLTRST_ is deasserted.
2. The default is latched from SW1.2 when PCH_PLTRST_ is deasserted
Table 6-40 Default Boot SPI Flash Write Enable
Address Offset: 0x41
Bit
Description
Default
Access
7:0
Default Boot SPI Flash Write enable/disable.
A write value 0xC3 enables the Boot Block. All other
values disables the Boot Block.
-
LPC: w
Table 6-41 Recovery Boot SPI Flash Write Enable
Address Offset: 0x42
Bit
Description
Default
Access
7:0
Recovery Boot SPI Flash enable/disable.
A write value 0xC3 enables the Flash. All other values
disables the Flash.
-
LPC: w