2 pca9555 internal register access, Table 6-37, Address control for pca9555 internal register – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 174: Table 6-38, Content of pca9555 internal register, Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
174
6.4.12.2 PCA9555 Internal Register Access
For debug purpose, the internal virtual PCA9555 registers can be read by the IPMC and the
Service Processor.
Table 6-37 Address Control for PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x34
CPU0 Device2 (Slave address 0x21): 0x36
CPU1 Device1 (Slave address 0x20): 0x3C
CPU1 Device1 (Slave address 0x21): 0x3E
Bit
Description
Default
Acces
s
2:0
Internal PCA9555 register address
0
r/w
7:3
Reserved
0
r
Table 6-38 Content of PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x35
CPU0 Device2 (Slave address 0x21): 0x37
CPU1 Device1 (Slave address 0x20): 0x3D
CPU1 Device1 (Slave address 0x21): 0x3F
Bit
Description
Default
Access
7:0
Content of PCA9555 register
0
r