2 telecom clock enable and routing register, Table 6-58, Telecom clock enable and routing register – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 187: Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
187
6.4.26.2 Telecom Clock Enable and Routing Register
6:2
Reserved
0
r
7
ACS device initialization status:
0: Ready for SPI access
1: Busy. The SPI initialization is still ongoing.
CPU_PWROK: 1
LPC: r
Table 6-57 ACS8225B Status/Control Register (continued)
Address Offset: 0x5F
Bit
Description
Default
Access
Table 6-58 Telecom Clock Enable and Routing Register
Address Offset: 0x60
Bit
Description
Default
Access
0
CLK3A Enable signal:
0: drive LCCB_CLK3A_EN low
1: drive LCCB_CLK3A_EN high
PWR_GOOD: 0 LPC: r/w
1
CLK3B Enable signal:
0: drive LCCB_CLK3B_EN low
1: drive LCCB_CLK3B_EN high
PWR_GOOD: 0 LPC: r/w
3:2
Reserved
0
r
5:4
Select clock source for signal LCCB_SYSCLK_OUT_A
00: LCCB_SYSCLK_IN_A
01: LCCB_SYSCLK_IN_B
10: LCCB_FPETH_RCLK1
11: LCCB_FPETH_RCLK1
PWR_GOOD: 0 LPC: r/w
7:6
Select clock source for signal LCCB_SYSCLK_OUT_B
00: LCCB_SYSCLK_IN_A
01: LCCB_SYSCLK_IN_B
10: LCCB_FPETH_RCLK1
11: LCCB_FPETH_RCLK1
PWR_GOOD: 0 LPC: r/w