Artesyn ATCA-7470 Installation and Use (October 2014) - Manual (Page 162)

Maps and Registers
ATCA-7470 Installation and Use (6806800P15K) 162
6.4.10.7 IPMC Watchdog Timeout Register
The IPMC SW sets the corresponding bit to signal an IPMC watchdog timeout event. When the
IPMC Watchdog Timeout bit is set from low to high, the corresponding bits in
Table "BIOS IPMC
Watchdog Timeout Register" on page 159 and Table "OS IPMC Watchdog Timeout Register" on
page 162 are set.
Table 6-24 OS IPMC Watchdog Timeout Register
Address Offset: 0x15
Bit Description Default Access
0 OS IPMC Watchdog Timeout:
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
1 OS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7:2 Reserved 0 r
IPMC clears the IPMC watchdog timeout bit to arm IPMC watchdog timeout event
recognition.
Table 6-25 IPMC Watchdog Timeout Register
Address Offset: 0x16
Bit Description Default Access
0 IPMC Watchdog Timeout:
0: No IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 IPMC: r/w
1 IPMC Pre-Timeout
0: No IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 IPMC: r/w
7:2 Reserved 0 r