19 cpld revision register, 20 spare signals status registers, Table 6-47 – Artesyn ATCA-7470 Installation and Use (October 2014) User Manual
Page 180: Cpld version and spare signal status register, Table 6-48, Spare signal status register, Maps and registers
Maps and Registers
ATCA-7470 Installation and Use (6806800P15K)
180
6.4.19 CPLD Revision Register
6.4.20 Spare Signals Status Registers
3
Control user LED output Signal LED_USER2_:
0: LED_USER2_ is driven high
1: LED_USER2 is driven low
0
LPC: r/w
IPMC: r
7:4
Reserved
0
r
Table 6-46 LED Status and Control Register (continued)
Address Offset: 0x50
Bit
Description
Default
Access
Table 6-47 CPLD Version and Spare Signal Status Register
Address Offset: 0x51
Bit
Description
Default
Access
2:0
CPLD Version. The CPLD uses the signals
CPLD_REV_BIT[2:0].
Ext.
r
7:3
Reserved 0
r
Table 6-48 Spare Signal Status Register
Address Offset: 0x52
Bit
Description
Default
Access
0
Reserved
0
r
1
Signal level of CPLD_SPARE
Ext
r
2
Signal level of
SH7757_2_FPGA_BMCRSVD<0>
Ext
r
3
Signal level of
SH7757_2_FPGA_BMCRSVD<1>
Ext
r