Altera DisplayPort MegaCore Function - Manual (Page 95)

This script executes the following commands:
• Generate the simulation files for the DisplayPort, transceivers, and transceiver reconfiguration IP
cores:
Arria 10 devices
•
qsys-generate a10_dp.qsys -syn -sim
•
qsys-generate gxb_rx.qsys -syn -sim
•
qsys-generate gxb_tx.qsys -syn -sim
•
qsys-generate gxb_tx_atx_pll.qsys -syn -sim
•
qsys-generate gxb_tx_reset.qsys -syn -sim
Arria V, Cyclone V, and Stratix V devices; (where <prefix> is av for Arria V devices, cv for Cyclone V
devices, and sv for Stratix V devices)
•
qmegawiz -silent
<prefix>
_xcvr_reconfig.v
•
qmegawiz -silent
<prefix>
_dp.v
•
qmegawiz -silent
<prefix>
_native_phy_rx.v
•
qmegawiz -silent
<prefix>
_native_phy_tx.v
• Merge the four resulting msim_setup.tcl scripts to create a single mentor/msim_setup.tcl:
Arria 10 devices
ip-make-simscript --spd=./a10_dp.spd --spd=./gxb_tx/gxb_tx.spd --spd=./gxb_rx/
gxb_rx.spd --spd=./gxb_tx_atx_pll/gxb_tx_atx_pll.spd --spd=./gxb_tx_reset/
gxb_tx_reset.spd --spd=./gxb_rx_reset/gxb_rx_reset.spd
Arria V, Cyclone V, and Stratix V devices; (where <prefix> is av for Arria V devices, cv for Cyclone V
devices, and sv for Stratix V devices)
ip-make-simscript --spd=./
<prefix>
_xcvr_reconfig.spd --spd=./
<prefix>
_dp.spd --spd=./
<prefix>
_native_phy_rx.spd --spd=./
<prefix>
_native_phy_tx.spd
• Compile and simulate the design in the ModelSim software:
vsim -c -do msim_dp.tcl
The simulation sends several frames of video after reconfiguring the DisplayPort source (TX) and sink
(RX) to use the HBR (2.7 G) rate. A successful result is seen by the CTS test automation logic’s CRC
checks. These checks compare the CRC of the transmitted image with the result measured at the sink. The
result is successful if the sink detects three matching frames.
Example 7-1: Example Successful Result
# Testing Link HBR Rate Training Pattern 1
# Testing Video Input Frame Number = 00
# Testing Link HBR Rate Training Pattern 2
# TX Frequency Change Detected, Measured Frequency = 135 MHz
# RX Frequency Change Detected, Measured Frequency = 135 MHz
# ...
# SINK CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40,
# SOURCE CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40,
# Pass: Test Completed
UG-01131
2015.05.04
Generate the IP Simulation Files and Scripts, and Compile and Simulate 7-7
DisplayPort IP Core Simulation Example Altera Corporation
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