Sink interfaces, Sink interfaces -6 – Altera DisplayPort MegaCore Function User Manual
Page 42
Parameter
Description
16-bpc RGB or YCbCr 4:4:4 (48 bpp)
Turn on to support 48 bpp decoding.
8-bpc YCbCr 4:2:2 (16 bpp)
Turn on to support 16 bpp decoding. Reserved for
future use.
10-bpc YCbCr 4:2:2 (20 bpp)
Turn on to support 20 bpp decoding. Reserved for
future use.
12-bpc YCbCr 4:2:2 (24 bpp)
Turn on to support 24 bpp decoding. Reserved for
future use.
16-bpc YCbCr 4:2:2 (32 bpp)
Turn on to support 32 bpp decoding. Reserved for
future use.
Support MST
Turn on to enable multi-stream support.
You have to turn on Enable GPU control to support
MST.
Max stream count
Select the maximum amount of streams supported
(1-4).
Sink Interfaces
The following tables summarize the sink’s interfaces. Your instantiation contains only the interfaces that
you have enabled.
Table 5-2: Controller Interface
Interface
Port Type
Clock Domain
Port
Direction
Description
clk
Clock
N/A
clk
Input
Clock for embedded
controller
reset
Reset
clk
reset
Input
Reset for embedded
controller
5-6
Sink Interfaces
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)