Altera DisplayPort MegaCore Function - Manual (Page 40)

Embedded DisplayPort (eDP) Support
The DisplayPort IP core is compliant with eDP version 1.3. eDP is based on the VESA DisplayPort
standard. It has the same electrical interface and can share the same video port on the controller. The
DisplayPort IP core supports:
• Full (normal) link training—default
• Fast link training—mandatory eDP feature
Sink Parameters
You set parameters for the sink using the DisplayPort parameter editor.
Table 5-1: Sink Parameters
Parameter Description
Device family Select the targeted device family—Arria V GX,
Arria V GZ, Cyclone V, or Stratix V—matches the
project device family.
Support DisplayPort sink Turn on to enable DisplayPort sink.
Maximum video output color depth Specify the video output interface port bits per color.
Determines top level video output port width (for
example, 6 bpc = 18 bits, 16 bpc = 48 bits).
RX maximum link rate Select the maximum link rate. 5.4 Gbps, 2.7 Gbps,
1.62 Gbps
Note: Cyclone V devices do not support 5.4
Gbps.
Maximum lane count Select the maximum lanes desired (1, 2, or 4).
Symbol input mode Specify how many symbols are transferred during
each clock cycle (dual or quad symbol), or RX
transceiver data width; dual (20 bits) or quad (40
bits).
Dual symbol mode saves logic resource but requires
the core to run at twice the clock frequency of quad
symbol mode. If timing closure is a problem in the
device, you should consider using quad symbol
mode.
5-4 Embedded DisplayPort (eDP) Support
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink
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