Altera DisplayPort MegaCore Function User Manual
Page 94
File Type
File
Description
vga_driver.v
VGA driver (generates a test image).
IP Catalog files
<prefix>
_
dp.v
IP Catalog variant for the DisplayPort IP Core.
<prefix>
_
xcvr_reconfig.v
IP Catalog variant for the transceiver reconfiguration
core.
<prefix>
_
native_phy_rx.v
IP Catalog variant for the RX transceiver.
<prefix>
_
native_phy_tx.v
IP Catalog variant for the TX transceiver.
Scripts
runall.sh
This script generates the IP simulation files and scripts,
and compiles and simulates them.
msim_dp.tcl
Compiles and simulates the design in the ModelSim
software.
Waveform
.do
files
all.do
Waveform that shows a combination of all waveforms.
reconfig.do
Waveform that shows the signals involved in reconfi‐
guring the transceiver.
rx_video_out.do
Waveform that shows the rx_video_out signals from
the DisplayPort IP core mapped to the CVI input.
tx_video_in.do
Waveform that shows the
tx_vid_v_sync
,
tx_vid_h_
sync
,
de
,
tx_vid_de
,
tx_vid_f
, and
tx_vid_
data[23:0]
signals at 256 pixels per line and 8 bpp, i.
Miscellaneous
files
readme.txt
Documentation for the simulation example.
edid_memory.hex
Initial content for the EDID ROM.
Generate the IP Simulation Files and Scripts, and Compile and Simulate
In this step you use a script to generate the IP simulation files and scripts, and compile and simulate them.
Type the command:
sh runall.sh
7-6
Generate the IP Simulation Files and Scripts, and Compile and Simulate
UG-01131
2015.05.04
Altera Corporation
DisplayPort IP Core Simulation Example