Altera DisplayPort MegaCore Function User Manual
Page 187
Location Name
Address
Without
Controller
With Controller
TEST_REQUEST
0×0218
—
Yes
TEST_LINK_RATE
0×0219
—
Yes
TEST_LANE_COUNT
0×0220
—
Yes
TEST_PATTERN
0×0221
Yes
—
TEST_H_TOTAL_LSB
0×0222
Yes
—
TEST_H_TOTAL_MSB
0×0223
Yes
—
TEST_V_TOTAL_LSB
0×0224
Yes
—
TEST_V_TOTAL_MSB
0×0225
Yes
—
TEST_H_START_LSB
0×0226
Yes
—
TEST_H_START_MSB
0×0227
Yes
—
TEST_V_START_LSB
0×0228
Yes
—
TEST_V_START_MSB
0×0229
Yes
—
TEST_HSYNC_LSB
0×022A
Yes
—
TEST_HSYNC_MSB
0×022B
Yes
—
TEST_VSYNC_LSB
0×022C
Yes
—
TEST_VSYNC_MSB
0×022D
Yes
—
TEST_H_WIDTH_LSB
0×022E
Yes
—
TEST_H_WIDTH_MSB
0×022F
Yes
—
TEST_V_HEIGHT_LSB
0×0230
Yes
—
TEST_V_HEIGHT_MSB
0×0231
Yes
—
TEST_MISC_LSB
0×0232
Yes
—
TEST_MISC_MSB
0×0233
Yes
—
TEST_REFRESH_RATE_NUMERATOR
0×0234
Yes
—
10-36
Sink-Supported DPCD Locations
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink Register Map and DPCD Locations
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)